As the demand for higher performance microcontrollers (MCUs) increases, semiconductor manufacturers are evaluating ways to design high performance MCUs, without sacrificing compatibility with low-end MCUs. Typically, the engineering investment in software development for microcontroller applications is significant. Thus, the design objective is to provide a family of MCUs wherein a higher performing MCU (i.e. 16-bit) is capable of running software generated for a lower performing MCU (i.e. 8-bit). Generally, meeting the stated objective imposes architectural constraints on the design of the higher performing MCU. In a typical 8-bit MCU design, the central processing unit (CPU) accesses only 64K bytes of memory. Generally, a significant performance enhancement is realized simply by expanding the addressable memory space, for example to 1M byte of memory, and thereby producing a 16-bit MCU capable of accommodating a larger memory space. In keeping with the stated objective, the design of a memory expansion scheme must allow the 16-bit MCU to execute source code generated for an 8-bit (existing) member of the MCU family.
Known 16-bit MCUs employ primarily two (2) memory expansion schemes, segmentation and simple bank switching. FIGS. 1A-B illustrate a known segmentation scheme 10 for memory expansion. In the segmentation scheme 10, a 16-bit logical segment base address is transferred into a 16-bit segment base register 12, via a logical address bus 18. The segment base address is shifted left four (4) bits to generate an extended 20-bit logical segment base address. A 16-bit logical offset address, stored in an offset register 14, is zero extended to produce a 20-bit logical offset address. After extension, the 20-bit logical segment base address is added to the 20-bit logical offset address by an adder 16, thereby generating a 20-bit (extended) physical address. The 20-bit physical address is transferred out to external memory (not shown), via physical address bus 17. Using the segmentation scheme 10, generates sixteen (16) 64K byte segments which can be placed on sixteen (16) byte boundaries. Most segmentation schemes require user intervention to update the segment base registers 12, and the offset registers 14, which may result in a performance penalty.
FIGS. 2A-B illustrate a simple bank switching scheme 20 for memory expansion. Generally, in the simple bank switching scheme 20, each memory bank is assigned a unique bank number. For example, the main memory may be sub-divided into sixteen (16) memory banks, whereby a 4-bit bank number is used to select a particular one of the sixteen memory banks. Accordingly, a 16-bit logical base address is transferred into an address register 22, via a logical address bus 25. A 16-bit offset address, stored in an offset register 23, is added to the 16-bit logical base address by an adder 26, and the result (16-bit logical address) is provided as an input to a concatenate logic block 27. The concatenate logic 27 receives a 4-bit logical memory bank address from a bank number register 24, and the 16-bit logical address from adder 26, and concatenates the two addresses, thereby providing a 20-bit (extended) physical address to physical address bus 28. The simple bank switching scheme 20 creates sixteen (16) 64K byte segments which can be placed on 64K byte boundaries. Generally, updating the value (memory bank address) stored in the bank number register 24 requires user intervention. Essentially, when the address calculation exceeds the boundary of the memory bank specified by bank number register 24, the simple bank switching scheme 20 will not allow the program to cross the memory bank boundary. Instead, the program will wrap-around within the specified memory bank. In order to cross a memory bank boundary, the user must first determine whether the address calculation crossed a memory bank boundary by performing a memory bank check, and then write a new memory bank number to the bank number register 24. Consequently, in the simple bank switching scheme 20, a performance penalty may occur when address calculations cross over bank boundaries. Thus, it is desirable to provide a memory expansion scheme capable of overcoming the foregoing problems.